- Joined
- 29 May 2002
- Messages
- 820
found this posted on some site...
playstation 3..
The CELL , chip that is expected to challenge the dominance of Intel and Advanced Micro Devices, was unveiled yesterday by Sony, Toshiba and IBM at International Solid State Circuits Conference in San Francisco.
The CELL at a Glance:
CELL is a Multi-Core Architecture
· Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
· Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design-views system memory as a 10-way coherent threaded machine
· 2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
· 234 million transistors
· Prototype die size of 221mm2
· Fabricated with 90nanometer (nm) SOI process technology
· Cell is a modular architecture and floating point calculation capabilities can be adjusted by increasing or reducing the number of SPUs
CELL is a Broadband Architecture
· Compatible with 64b Power ArchitectureTM
· SPU is a RISC architecture with SIMD organization and Local Store
· 128+ concurrent transactions to memory per processor
· High speed internal element interconnect bus performing at 96B/cycle
CELL is a Real-Time Architecture
· Resource allocation (for Bandwidth Management)
· Locking caches (via Replacement Management Tables)
· Virtualization support with real time response characteristics across multiple operating systems running simultaneously
CELL is Security Enabled Architecture
· SPUs dynamically configurable as secure processors for flexible security programming
CELL is a Confluence of New Technologies
· Virtualization techniques to support conventional and real time applications
· Autonomic power management features
· Resource management for real time human interaction
· Smart memory flow controllers (DMA) to sustain bandwidth
playstation 3..
The CELL , chip that is expected to challenge the dominance of Intel and Advanced Micro Devices, was unveiled yesterday by Sony, Toshiba and IBM at International Solid State Circuits Conference in San Francisco.
The CELL at a Glance:
CELL is a Multi-Core Architecture
· Contains 8 SPUs each containing a 128 entry 128-bit register file and 256KB Local Store
· Contains 64-bit Power ArchitectureTM with VMX that is a dual thread SMT design-views system memory as a 10-way coherent threaded machine
· 2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
· 234 million transistors
· Prototype die size of 221mm2
· Fabricated with 90nanometer (nm) SOI process technology
· Cell is a modular architecture and floating point calculation capabilities can be adjusted by increasing or reducing the number of SPUs
CELL is a Broadband Architecture
· Compatible with 64b Power ArchitectureTM
· SPU is a RISC architecture with SIMD organization and Local Store
· 128+ concurrent transactions to memory per processor
· High speed internal element interconnect bus performing at 96B/cycle
CELL is a Real-Time Architecture
· Resource allocation (for Bandwidth Management)
· Locking caches (via Replacement Management Tables)
· Virtualization support with real time response characteristics across multiple operating systems running simultaneously
CELL is Security Enabled Architecture
· SPUs dynamically configurable as secure processors for flexible security programming
CELL is a Confluence of New Technologies
· Virtualization techniques to support conventional and real time applications
· Autonomic power management features
· Resource management for real time human interaction
· Smart memory flow controllers (DMA) to sustain bandwidth
